As is well known by those skilled in the art, a continuing goal in manufacturing and production of semiconductors is a reduction in size of components and circuits with the concurrent result of an increase in the number of circuits and/or circuit elements such as transistors, capacitors, etc., on a single semiconductor device. This relentless and successful reduction in size of the circuit elements has also required reduction in the size of the conductive lines, connecting devices and circuits. However, as the individual circuits and conducting lines are designed to be smaller and smaller, the number of circuits and connecting lines is increasing. This increase in numbers simultaneously raises the opportunity for more open circuits, more short circuits and other failures. The smaller size also increases the difficulty of identifying problem areas and/or failures such as short circuits and open circuits. As will be appreciated by those skilled in the art, these difficulties have led to the development of the OBIRCH testing techniques such as for example, described in Proceedings of the ATS (Asian Testing Symposium) 1997 Nov. 17, AKITA, pp. 214-219 (1997).
Aluminum is one of the materials commonly used as the metal interconnect lines and silicon oxide is commonly used as the dielectric. Deterioration of the reliability of aluminum interconnection lines has become more serious with the progressive miniaturization of semiconductor integrated circuits and increase in interconnection levels of semiconductor integrated circuits. Deterioration of the reliability of aluminum interconnection lines is attributable to increase in current stresses and mechanical stresses induced in aluminum interconnection lines.
While the size of aluminum interconnection lines is on the submicron order, currents that flow through aluminum interconnection lines are on the order of several hundred microamperes and current density is as high as the order of 105 A/cm2. Further, mechanical stresses are induced in interconnection lines when the semiconductor integrated circuit is subjected to heat treatment in the LSI manufacturing process.
Such stresses induced in the interconnection lines cause the migration of aluminum atoms, electromigration or stress migration, which forms voids in the interconnection lines. These voids increase the resistance of the interconnection lines and, in the worst case, break the interconnection lines.
However, newer manufacturing techniques now favor copper as the metal for interconnect lines and various low K materials (organic and inorganic) are favored as the dielectric material. Aluminum interconnects may be formed by depositing a layer of aluminum and then using photoresist, lithography, and etching to leave a desired pattern of aluminum lines, the formation of copper interconnect lines are typically formed by a process now commonly referred to as a Damascene process. The Damascene process is almost the reverse of etching, and simply stated a trench, canal or via is cut, etched or otherwise formed in the underlying dielectric and is then filled with metal (i.e., copper).
Unfortunately, although copper has the advantages discussed above, it readily diffuses into dielectric material used in the manufacture of semiconductor devices, and it diffuses especially easily into silicon dioxide. Diffusion of copper into the dielectric materials of a semiconductor device can cause serious reliability problems including electrical shorts. Therefore, it is typical to form a barrier layer between the copper used for conductors and leads and the dielectric material of a semiconductor device. Typical barrier layers may be formed of Ta (tantalum), TaN (tantalum nitride), Ti (titanium), TiN (titanium nitride) and various combinations of these metals as well as other metal. The barrier layer is typically formed on the bottom and sidewalls of the trenches and vias of the copper interconnects to prevent the copper from diffusing into the surrounding silicon dioxide as other dielectric material. A layer of silicon nitride is then typically deposited as a cover layer over the complete structure including the conductor areas and the dielectric layer before another layer or level of dielectric structure is deposited.
Accordingly, whether the integrated circuits (IC's) are fabricated using copper or aluminum interconnecting lines, the detection and observation of the frequency and positions of voids or shorts in the interconnecting lines, whether copper or aluminum, are essential to the reliability of integrated circuits.
Furthermore, as the size of the integrated circuits continues to decrease, the voltage levels for operating the individual elements has also decreased. Consequently, background noise and instability or drift of the power supplies used to test the circuits has a growing adverse effect on the ability to successfully test the IC's and to identify and locate the problems.
Therefore it would be advantageous to reduce the effects of background noise and power supply drift caused by the power supplies used during testing.